Referring to FIG. 1, an integer-N phase locked loop (PLL) 100 typically is locked when the frequency (fb) of its feedback signal 155 is equal to the frequency (fr) of an incoming clock signal 105. Therefore, the frequency (fvco) of the voltage controlled oscillator (VCO) 140 in the loop 100 equals N*fr, where N is the divide-by ratio of a /N divider 150, the frequency resolution at the VCO 140 is fr, and the bandwidth of the PLL loop is usually designed less than fr/10. To improve frequency resolution, a relatively small frequency (fr) of the incoming clock signal 105 is used. However, using a relatively small fr forces the loop bandwidth to be reduced. In PLL design, this phenomenon is known as “the resolution vs. bandwidth battle.”
FIG. 1 shows a traditional implementation of an integer-N phase locked loop circuit 100 using a feedback mechanism. A phase detector 110 detects the frequency and phase difference between the input clock signal 105 and feedback signal 155, and outputs an offset signal 115 to a charge pump 120. The charge pump 120 converts the offset signal 115 into a current signal that can be fed to a low pass filter 130. Subsequently, the loop filter 130 smoothes this signal, and outputs an adjustment signal 135 to a voltage controlled oscillator (VCO) 140. The VCO 140 receives the signal 135 from the low pass filter 130 and outputs a clock signal 145 to a divide-by-N divider 150, where N is an integer and is constant. The divider 150 outputs a feedback signal 155 to the phase detector 110 for a frequency and phase comparison with the clock signal 105.
Generally, fractional-N phase locked loops, which have been known for several decades, are used most often to deal with the phenomenon and/or problem of a reduced loop bandwidth when using a relatively small fr. Typically, there are several ways to achieve a fractional-N result.
Referring to FIG. 2, methods used to achieve fractional-N results included a dual modulus prescaler 160. In theory, with this method, there are virtually two dividers “N” and “A”, and one dual modulus prescaler M/M+1, in the divider 160. As is known in the art of clock synthesis, the final output frequency (fout) is related to the input frequency fr by the following equation:fout=fr*(M*N+A)  (1)
In later years, multi-modulus dividers controlled by sigma-delta modulators outdated the dual modulus designs due to the capability of randomizing the fractional spurs and moving them to a higher frequency band. In both of the above approaches, there is a phase jump of one VCO period when the divide ratio of the divider 160 switches.
In recent years, multi-phase dividers have drawn attention from researchers since they can reduce the phase jump to less than one VCO period. Subsequently, a multi-phase divider was used in a fractional-N PLL (J. Craninckx, M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7 μm CMOS,” IEEE J. Solid-State Circuits, Vol. 31, No. 7, pp. 890-897, 1996). The dual modulus 4/5 prescaler is achieved through phase rotation within a 4-phase selection circuit. In another example, multi-phasing is used to produce a resolution of 1/8 VCO period. Furthermore, the 1/8 VCO period resolution was achieved with an additional capability of self-calibrating the mismatch between phases (see C. Park, O. Kim and B. Kim, “A 1.8 GHz self-calibrated phase-locked loop with precise I/Q matching,” IEEE J. Solid-State Circuits, vol. 36, pp. 777-783, May 2001).
Presently, there are cases of combining multi-modulus and multi-phase techniques and using sigma-delta modulation on the multi-modulus divider (e.g., divider 160 in FIG. 2) to achieve low phase noise. Furthermore, there have been cases in which a glitch-free phase switching circuit is used as a 15/16 prescaler. The glitch-free phase switching circuit is achieved by only allowing phase rotation in a certain direction (e.g., backwards). Another example includes using a 1/8 fractional divider in a digital PLL.
In all of the above implementations, regardless of whether a multi-modulus or multi-phase divider 160 was used, the divide ratio is time-varying, and the output waveform of the divider 160 is not periodic. In other words, the divide ratio varies from time to time (e.g., is not constant), and the clock pulse is not a periodic signal. Thus, fractional spurs occur. Unfortunately, fractional spurs are a price that one pays for improved frequency resolution.
To obtain better frequency resolution (fr), two integer-N PLLs may be cascaded together, as shown in FIG. 3. For the first PLL 200-1, the frequency (fout1) at node 265 after the M1 divider 260 can be expressed as (N1/M1)*fr, where N1 is the integer value of divider 250 and M1 is the integer value of divider 260. This frequency fout1 is used as the reference frequency of the second PLL 200-2. Thus, the output frequency fout2 from the second PLL 200-2 can be expressed as (N2/M2)*fout1, which is equal to (N1*N2/(M1*M2))*fr, where N2 is the integer value of divider 250′ and M2 is the integer value of divider 260′.
This “Discussion of the Background” section is provided for background information only. The statements in this “Discussion of the Background” are not an admission that the subject matter disclosed in this “Discussion of the Background” section constitutes prior art to the present disclosure, and no part of this “Discussion of the Background” section may be used as an admission that any part of this application, including this “Discussion of the Background” section, constitutes prior art to the present disclosure.